1) Field of the Invention
This invention relates generally to fabrication semiconductor memory devices and particularly to the structure of a one transistor (1T) Static Random Access Memory (SRAM) cell.
2) Description of the Prior Art
FIG. 1 shows a schematic of a one transistor (1T) Static Random Access Memory (SRAM) cell. The 1T SRAM is designed for high speed and low cost logic products. However, the inventors have found that the 1 T SRAM cell has performance degradation that can be reduced.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,686,336 (Lee) shows a 4T SRAM layout. U.S. Pat. No. 6,078,087 (Huang et al.) and U.S. Pat. No. 5,953,606 (Huang et al.) shows TFT SRAM layouts.